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PEGMA Rev0 Schematic

This week I sent the first revision of the PEGMA board off to Advanced Circuits for manufacture. The final features onboard are as follows:

  • 5 input boost power supplies (1.4V – 6V, 1.5A)
  • 3 output boost power supplies (5V – 14V, 1.5A)
  • 8 peripheral buck power supplies (1.8V – 5.5V, 500mA)
    • Domain 0: Microcontroller only (STM32F205VG), used for traditional DVFS
    • Domain 1: Energy usage measurement and allocation
    • Domain 2: SRAM (IS61WV51216) voltage modulation
    • Domain 3: SPI devices
      • 2x 64K EEPROM chips (Microchip 25AA512)
      • Humidity / temperature sensor (Honeywell HIH-6130)
      • SDCard (Swissbit S-200U)
    • Domain 4: External battery / supercap charging circuit
    • Domain 5: Communications devices
      • MAX232 chip with 2x RS232 ports
      • ADM3491 for full duplex RS485
      • XBEE module for 802.15.4 communication
      • RN42XV module for bluetooth communication
    • Domain 6: 8x LED indicators and 3x Pushbutton inputs
    • Domain 7: 4x Relay output and 1x external voltage output
  • USB slave power / communications
  • Selectable capacitance on the buck peripheral voltage rail.

The devices of Domain 1 are configured in such a way that the input current and voltage to each domain are simultaneously sampled. This allows the user to measure the efficiency of each domain in real time and make decisions about where energy is being generated and spent.

My first experiment will be to determine if savings are possible by decreasing the voltage to the EEPROM chips in Domain 3 during the page write / erase time. This time takes approximately 5ms and is not specified to be voltage dependent. Therefore significant savings may be possible by writing data at the maximum transmission speed and then decreasing the peripheral voltage to the minimum required for the remaining 5ms.

PEGMARev0 pegma

 

The schematic can be downloaded in PDF format here: PEGMARev0.

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