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Demultiplexers, Decoders and Addressable Latches

Recently I ran into a problem while working on the PEGMA project and the solution took me a long time to solve. I thought I would take this opportunity to do a bit of 74 series logic review. Let’s say for instance that you had a situation where you wanted to select / de-select some number of enable pins while keeping the number of input I/O at a minimum:


Naturally, one thinks of the decoder circuit above (and grounding the G1 and G2 inputs). The problem with this circuit is that in this case only one circuit can be asserted (low) at a time as is evidenced by the following truth table (this is for a 4514 so the logic is opposite, but the point stands):



So what options do we have if we want to select multiple and arbitrary enable lines while keeping input I/O to a minimum? You could build your own, using flip flops and NAND gates, but you would quickly find this to be expensive in real estate, power consumption and time! After quite a bit of research I found a member of the 74 series logic family that will do the job. The 75HC259 is an “Addressable Latch”. The chip uses the address lines to assert an output into the state designated by D:



The particular device that I chose has a wide input voltage and the full data sheet can be found here. There are are few drawbacks. First, this device is only a 3-8 addressable latch. As far as I can tell, there are no 4-16 addressable latches in existence and therefore I will be needing to use two of them.

Eventually I settled on a circuit that looks like this:



There is an extra line of I/O vs the original decoder circuit (which wouldn’t have worked). However, this extra line provides faster access to assert and de-assert signals that have the same address.


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